1. Field of the Invention
The present invention relates generally to electrical interconnections and, more particularly, electrical interconnections having improved reliability when, for example, they are formed between two components exhibiting different coefficients of thermal expansion (CTE).
2. State of the Art
Various types of electrical interconnections are used to operably couple one or more components of an electrical device. For example, semiconductor devices are often electrically connected to other components such as carrier substrates or other higher-level packaging through solder-type interconnections. While numerous types of solder-type and other electrical interconnections exist, one technique which has become conventional in the industry includes flip chip bonding which includes a variant known as controlled collapse chip connection or “C4” bonding. With the C4 technique, individual masses of solder are provided on the contact pads of the semiconductor device or the carrier substrate prior to assembly of the two components. During assembly, the solder masses are reflowed by bringing them to an elevated reflow temperature sufficient to melt or at least partially melt the solder. The assembly is then cooled, leaving soldered electrical interconnections between the contact pads of the chip and corresponding contact pads of the carrier substrate. In conventional interconnecting techniques wherein the electrical interconnections are formed in an arrayed pattern, such as in ball grid array (BGA) or column grid array (CGA) devices, the contact pads (also referred to as bond pads) of the semiconductor device correspond locationally and are aligned with a mirrored array of contact or terminal pads on the carrier substrate. The term “contact pads” as used herein pertaining to semiconductor devices includes not only bond pads but also I/O connections for the device rerouted from bond pad locations into, for example, an array.
Solder bonds such as those described above are conventionally subjected to thermally induced fatigue stress under normal operating conditions. For example, electrical power supplied to a packaged semiconductor device and signals input to and output therefrom, as well as transitions between passive and active operational states of the semiconductor device, each tend to cause a thermal cycling of the package as temperatures within the package rise and fall. Such a semiconductor device package, including the electrical interconnections associated therewith, also experiences thermal cycling during various fabrication and testing processes, including, without limitation, burn-in of the semiconductor device.
It is often the case that a semiconductor device and the other electronic component to which it is attached for operation are formed of different materials and, therefore, exhibit different CTEs. Thus, different components of a given electronic device assembly may expand or contract at varied and substantially independent rates, which often results in thermally induced stress in the electrical interconnections (e.g., the solder joints) formed between such components. For example, a semiconductor device may expand and contract at a first rate while a carrier substrate to which it is attached through the electrical interconnections may expand and contract at another, different rate. In such a case, the electrical interconnections (e.g., solder-type connections) which also form a mechanical interconnection of the semiconductor device to the carrier substrate, are placed in repeated cycles of tension and/or compression. Such cycles of stress eventually lead to a fatigue-type failure in one or more of the electrical interconnections, which may cause an open circuit and operation failure of the electronic device assembly.
Even in the case where the connected components (e.g., the semiconductor device and the carrier substrate) exhibit similar CTES, heat transfer within the electronic device assembly components and between the assembly and the ambient environment will not necessarily be uniform due to the configuration of the assembly and differing heat transfer rates of portions of each of the components thereof and, thus, different components of the electronic device assembly will still likely experience differing relative rates of expansion and contraction.
Various attempts have been made to alleviate fatigue-related failures in electrical connections. One such attempt has been to provide a mechanically stronger interconnection such as with ceramic column grid array (CCGA) technology. CCGA technology relies on solder columns formed of a 90Pb (lead)—10Sn (tin) solder composition (90% lead and 10% tin). Such a composition exhibits a high melting temperature and thus is used in conjunction with ceramic materials (e.g., substrates) which may be subjected to elevated temperatures during various process steps. Furthermore, individual columns are conventionally attached to the contact pads of the chip or carrier substrate with a different solder composition. For example, at least one end of a solder column may be attached to an associated contact pad using a 63Sn-37Pb solder composition because of the latter's lower melting point. However, the melding of two different solder compositions creates the possibility of discontinuities and localized stresses at the interface between the solder column and the contact pad.
Furthermore, the use of different materials and processing equipment required to form CCGA-type connections can increase the fabrication costs of electronic and semiconductor devices.
Another technique which has been used in an attempt to alleviate temperature-induced fatigue failures of electrical interconnections is to draw out, or elongate, a solder-type connection under the premise that a solder connection having a narrowed, or necked, midsection relieves stress concentrations at the solder-contact pad interface. Such a technique is taught in U.S. Pat. No. 6,335,222 to DiStefano, issued Jan. 1, 2002.
The DiStefano patent teaches a technique of joining two components, each having a plurality of contact pads on a surface thereof, by disposing a mass of solder between corresponding contact pads of the two components and heating the solder to a temperature above the recrystallization temperature thereof. With the solder in a partially liquid state, the two components are drawn apart, or displaced from one another in a direction which is transverse to the plane of the array of solder connections, to elongate each of the solder connections. The drawing apart or relative displacement of the two components may be accomplished by forming a seal between the peripheries of the two components and then introducing a fluid pressure between the opposing surfaces of the components.
The DiStefano patent further discloses that in lieu of, or in addition to, drawing the two components from one another in a direction transverse to the plane of the array of solder connections, the two components may be relatively displaced in a direction which is parallel with the plane in which the array of solder connections is disposed. Such a parallel displacement causes a shift in the angle at which the elongated solder connection is formed. The DiStefano patent does not appear to teach any substantial benefits to skewing the angle of the elongated solder connections, but rather seems to simply consider such as an alternative or additional technique for forming the elongated solder connection having a thinned midsection.
It is noted that in forming an elongated solder connection having a skewed angle according to the method taught by DiStefano (i.e., through the relative displacement of components in a parallel direction with respect to the plane in which the array of solder connections is formed), all the solder connections are formed to exhibit similar angles relative to the plane parallel to the array of connections as well as exhibiting a common “azimuth” or orientation relative to the same plane.
Furthermore, regardless of whether the two components are drawn apart from one another or shifted horizontally relative to one another, both components must be held captive during the assembly process (at least until the solder is sufficiently hardened) and additional equipment having precision dimensional displacement control would likely be required to effect the displacement process. Such is contrary to more conventional solder connection techniques wherein typically only one of the components is required to be held captive during formation of the solder connections.
In view of the shortcomings in the current state of the art, it would be advantageous to provide a new electrical interconnection and method of forming such an electrical interconnection which improves reliability, particularly with respect to thermally induced fatigue developed within assemblies of electronic components.
It would further be advantageous if such an electrical interconnection and associated method of fabrication could be easily incorporated into existing manufacturing processes without requiring new or additional equipment or additional process expenses. Similarly, it would be advantageous if such an electrical interconnection could be formed using materials and material compositions conventionally used in the art.